From: "Mark A. Greer" <mgreer@mvista.com> This patch allows the Freescale Sandpoint to perform soft reboots. A write of 0x00 to the Winbond's Chip Select Control Register was clearing the Upper BIOS Chip Select Enable bit which unmaps the boot flash. The comment associated with the write noted that it was enabling the RTC and Keyboard address locations, but the bits in question (1 and 0) are reserved when the Winbond chip is in PowerPC mode. Also, the bits are 1 for enable, 0 for disable, therefore the original code was actually disabling the address locations. The patch also corrects errors in the definitions of 2 configuration bits in the Tundra Tsi107 bridge's MAPB Options register. Signed-off-by Randy Vinson <rvinson@mvista.com> Signed-off-by Mark A. Greer <mgreer@mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> --- 25-akpm/arch/ppc/platforms/sandpoint.c | 7 ------- 25-akpm/include/asm-ppc/mpc10x.h | 4 ++-- 2 files changed, 2 insertions(+), 9 deletions(-) diff -puN arch/ppc/platforms/sandpoint.c~ppc32-fix-sandpoint-soft-reboot arch/ppc/platforms/sandpoint.c --- 25/arch/ppc/platforms/sandpoint.c~ppc32-fix-sandpoint-soft-reboot Wed Mar 23 15:56:19 2005 +++ 25-akpm/arch/ppc/platforms/sandpoint.c Wed Mar 23 15:56:19 2005 @@ -202,13 +202,6 @@ sandpoint_setup_winbond_83553(struct pci 0x48, /* ISA-to-PCI Addr Decoder Control */ 0xf0); - /* Enable RTC and Keyboard address locations. */ - early_write_config_byte(hose, - 0, - devfn, - 0x4d, /* Chip Select Control Register */ - 0x00); - /* Enable Port 92. */ early_write_config_byte(hose, 0, diff -puN include/asm-ppc/mpc10x.h~ppc32-fix-sandpoint-soft-reboot include/asm-ppc/mpc10x.h --- 25/include/asm-ppc/mpc10x.h~ppc32-fix-sandpoint-soft-reboot Wed Mar 23 15:56:19 2005 +++ 25-akpm/include/asm-ppc/mpc10x.h Wed Mar 23 15:56:19 2005 @@ -115,8 +115,8 @@ #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ #define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ -#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x80 /* PCI_COMPATIBILITY_HOLE */ -#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x40 /* PROC_COMPATIBILITY_HOLE */ +#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ +#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ /* Define offsets for the memory controller registers in the config space */ #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ _